1. Field of the Invention
The present invention relates to a process for formation of a spacer using an oxide shield. The spacer formation process is formed on a poly stud planarized to a pad nitride on oxide formed on top of the poly prior to the pad nitride strip. After a pad nitride removal step, the poly is etched back and nitride is deposited conformally followed by an anisotropic nitride RIE etch, so as to enable the oxide to protect the nitride underneath from being etched.
2. Description of the Prior Art
In present day requirements for ultra large scale integration (ULSI) for high density semiconductor devices, there is a requirement that the submicron features be approximately 0.25 microns and smaller in order to provide increased circuit speeds. The increased requirements for faster circuit speeds coupled with increased density also demand device features characterized by high precision and uniformity.
With this as a backdrop, it is pointed out that conventional semiconductor devices physically comprise a substrate and electrically isolated regions termed active regions, in which individual circuit components are formed. The electrical isolation of these active regions may be accomplished by thermal oxidation of the semiconductor substrate, that is, monocrystalline silicon or an epitaxial layer is formed, bound by active regions.
For example, a typical isolation region is known as a trench isolation, and in this structure, shallow trenches are etched in the substrate, and an oxide liner is thermally grown on the trench walls, whereupon the trench is refilled with an insulating material. The structure resulting is called a shallow trench isolation (STI) structure. The active region of this structure comprises source/drain regions formed in the semiconductor substrate by the implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween.
The gate electrode controls the turn-on and turn-off of each transistor. After implantation of the substrate is completed, titanium silicide, CoSi or NiSi may be formed on the gates and source/drain reunions to reduce the sheet resistance in these areas to provide increased performance. The trench formation generally comprises growing a pad oxide layer on the substrate and depositing a barrier nitride layer thereon. Next, a photoresist mask is applied to delineate the trench areas. The exposed portions of the nitride layer are etched away followed by the pad oxide layer. Etching is continued into the substrate to form a shallow trench, and when the etching of the trench is completed, the photoresist is stripped off the nitride layer.
Thereafter, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality, whereupon the trench is then refilled with an insulating material such as silicon dioxide and the surface is planarized by CMP and the nitride and pad oxide are stripped of the active areas to complete the trench isolation structure.
Next, well implants may be formed by and masking and ion implantation, whereupon the surface is cleaned, and a gate oxide layer is formed and a polycrystalline silicon layer is deposited and etched to form a gate electrode. Lightly-doped drain or other source/drain implants may thereafter be formed by appropriate masking and ion implantation. After the lightly-doped drain (LDD) is formed self aligned to the gate conductor, a conformal layer of oxide or nitride may be deposited and anisotropically etched to leave spacers along the edges of the gates to prevent a later applied heavy-dose source/drain implant from completely overlapping the lightly-doped area next to the gates or other shallow source/drain regions. Ion implantation may then be conducted to form source/drain regions with later activation to complete the transistor structure.
A titanium silicide, CoSi or NiSi layer may then be formed on the gates and source/drain regions by sputtering the silicide and rapid thermal annealing. If it is desirable to create unsilicided gate and source/drain regions, a resistor protective oxide is deposited prior to sputtering the silicide on the substrate and portions of the resistor protective oxide may be etched away. After the resist is etched and titanium is deposited, the oxide remaining prevents formation of silicide in the desired areas.
It is desirable when making the STI structure to have the uppermost surface of the substrate to be flush with the uppermost surface of the oxide filling the trench at the edges of the trench to maximize performance of the completed device and to obtain a flat topography for later processing steps, especially photolithographic processing to thereby facilitate formation of small features with accuracy.
During formation of the spacer, which is the result of an anisotropic etch of a material deposited conformal over a step process prior to the deposition, it has been found that the spacer formation is strongly dependent on the structure (e.g. taper) of the step.
U.S. Pat. No. 6,303,452 B1 discloses a method for making a transistor spacer etch pin point structures. The invention is incorporated into a method for forming an integrated circuit, and the integrated circuit formed thereby, by forming a gate over a portion of a substrate. A dielectric layer is formed over the gate and a portion of the substrate, and oxide sidewalls spacers are formed on the sides of the gate and on top of the dielectric layer.
A method of etching silicon nitride spacers beside a gate structure is disclosed in U.S. Pat. No. 6,277,700 B1. The process entails:
a) providing a gate electrode over a gate oxide layer on a substrate; providing a liner oxide layer over the substrate and the gate electrode; providing a silicon nitride layer over the liner oxide layer;
b) anisotropically etching the silicon nitride layer forming spacers by performing a nitride etch recipe in a plasma etcher; the nitride etch recipe comprising a main etch step and an over etch step;
(b1) the main etch step comprising the conditions: a Cl2 flow between 35 and 55 molar %, a He flow between 35 and 55 molar %, and a HBr flow between 7.5 and 12.5 molar %.
A method of forming a trench edge spacer formation is disclosed in U.S. Pat. No. 6,005,279. The method comprises:
forming a trench opening and thermally growing an oxide liner on an internal surface of the trench and abutting a main surface of the substrate or epitaxial layer; filling the trench with an insulating material; depositing a protective layer having an etch rate less than the oxide liner and the insulating material on the main surface covering an exposed upper edge of the trench where the main surface abuts the liner; and anisotropically etching the protective layer to form a protective spacer on the trench edge.
There is a need in the art to improve the spacer formation on a poly stud planarized to pad nitride during formation of a semiconductor structure.
It is an object of the present invention during formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper) to provide improved spacer formation on a poly stud planarized to pad nitride where an oxide is formed on top of the poly prior to the pad nitride strip. After pad nitride removal, the poly is etched back and nitride is deposited conformal followed by anisotropic nitride RIE etch, so that the oxide protects the nitride underneath from being etched.